$(15$ points$)$ A processor has an address bus of $10$ bits $(A_9..A_0),$ a data bus

of $8$ bits $(D_7..D_0)$ and Read $($RD$)$ and Write $($WR$)$ outputs. Four memory

chips with Read $($RD$),$ Write $($WR$),$ Chip Select $($CS$),8-$bit address lines

and $8-$bit data buses are given. Provide the interface of these memory chips

to the processor so that each memory chip has a distinct address range to

realize a total of $1KB.$

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$(25$ points$)$ Given the sequential circuit of Fig. $1,$ work out the state

transition table and the finite state machine diagram.