$<1\mathrm{.}6>$ Consider two different implementations of the ARM instruction set architecture. The instructions can be divided into four classes according to their CPI $($class A$,$ B$,$ C$,$ and D$).$ For example think of A as number of cycles to complete as Arithmetic Instructions, B for Branch Instructions, C for Load$/$Store instructions and D for floating point Math. Each instruction class will have a different execution time expressed in number of cycles.

Assume a dynamic $($measured at runtime$)$ instruction count of $1\mathrm{.}0$E$6$ total instructions. The following tables contain the CPI and Percentage number for each instruction class, for Processor P$1$ and Processor P$2$: