Question: 1. Consider the following C program. It will run on a processor of a data cache and an instruction cache. For this question, ignore instruction

 1. Consider the following C program. It will run on a

1. Consider the following C program. It will run on a processor of a data cache and an instruction cache. For this question, ignore instruction cache miss (the instruction cache size is more than enough). /1 double is 8-byte double X [1024] double sum = 0.0; double max = DBL MIN; // DBL MIN ?s minimum value for double for (int ? = 0; i max ) maxX[i] Assume that the start address of the array is a multiple of 32. a. Assume the cache is 16 KB, direct mapped, and of 32-byte blocks. How many cache misses will happen? Explain your result. b. Now assume the cache is 4 KB, direct mapped, and of 32-byte blocks. How many cache misses will happen? Explain your result. Pay attention to the difference in the cache size. c. This question continues sub-question b). Revise the code to reduce the number of cache misses. Write down the code in the space below. You don't have to copy the declarations. 1. Consider the following C program. It will run on a processor of a data cache and an instruction cache. For this question, ignore instruction cache miss (the instruction cache size is more than enough). /1 double is 8-byte double X [1024] double sum = 0.0; double max = DBL MIN; // DBL MIN ?s minimum value for double for (int ? = 0; i max ) maxX[i] Assume that the start address of the array is a multiple of 32. a. Assume the cache is 16 KB, direct mapped, and of 32-byte blocks. How many cache misses will happen? Explain your result. b. Now assume the cache is 4 KB, direct mapped, and of 32-byte blocks. How many cache misses will happen? Explain your result. Pay attention to the difference in the cache size. c. This question continues sub-question b). Revise the code to reduce the number of cache misses. Write down the code in the space below. You don't have to copy the declarations

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