[15 pts] Consider the following C program. It will run on a processor of a data cache and ar instruction cache. For this question, ignore instruction cache miss (the instruction cache size is more than enough) 3. // double is 8-byte double Xr10241 double sum - 0.0; double max DBL MIN; // DBL MIN ?s minimum value for double sum +-- x [i] ; if (X[d] > max ) x [i] ; max = Assume that the start address of the array is a multiple of 32. [5 pts] Assume the cache is 16 KB, direct mapped, and of 32-byte blocks. How many cache misses will happen? Explain your result. a. b. [5 pts] Now assume the cache is 4 KB, direct mapped, and of 32-byte blocks. How many cache misses will happen? Explain your result. Pay attention to the difference in the cache size c. [5 pts] This question continues sub-question b). Revise the code to reduce the number of cache misses. Write down the code in the space below. You don't have to copy the declarations