Create the VHDL files provided by in appendix A adding them to your VHDL

project $($Remember you need only one project for the entire course$).$

$2.$ Fully comment the code provided in appendices A and B$.$

$3.$ Obtain the RTL schematics of the Instruction Fetch stage, and each of its

components. Write down the differences between these schematics and the ones

in Figure $1.$

$4.$ Translate the code shown in the listing $5\mathrm{.}1$ to binary using the basic instruction

formats shown in Figure $3$ and fill the two leftmost columns of Table $1,$ with the

register letters u$,$ v$,$ w$,$ x$,$ y resolved to their equivalent numbers as explained

below.