Create the VHDL files provided by in appendix A adding them to your VHDL

project $($Remember you need only one project for the entire course$).$

$2.$ Fully comment the code provided in appendices A and B$.$

$3.$ Obtain the RTL schematics of the Instruction Fetch stage, and each of its

components. Write down the differences between these schematics and the ones

in Figure $1.$

$4.$ Translate the code shown in the listing $5\mathrm{.}1$ to binary using the basic instruction

formats shown in Figure $3$ and fill the two leftmost columns of Table $1,$ with the

register letters u$,$ v$,$ w$,$ x$,$ y resolved to their equivalent numbers as explained

below.

$\{$Listing $5\mathrm{.}1$: Assembly Code

start: lw Ru$,4($R$0)$

lw Rv$,8($R$0)$

add Rw$,$ Ru$,$ Rv

sub Rx$,$ Ru$,$ Rv

sw Rx$,12($R$0)$

slt Ry$,$ Ru$,$ Rv

beq Ru$,$ Ru$,$ start

where u is the first non$-$zero digit of your id number, v is the second nonzero digit of

your id number, w is the third nonzero digit of your id number, and x is the fourth non

zero digit of your id number, and y is a random number between $10$ and $31.$

$5.$ Create a test bench file and run a simulation showing the operation of the instruction

fetch stage. You must first load your program $($Listing $5\mathrm{.}1)$ binary instructions obtained

in the previous step, into the instruction memory in order to have instructions to fetch.

To do that follow the sample test bench file shown in appendix B$.$ Your simulation

should look similar to the one in Figure $4,$ only that it should include all instructions to

be loaded and fetched. Explain the results of that simulation using annotations on the

timing diagram.

Figure $4$: IF simulation timing diagram for $2$ instructions. Source: Generated using Xilinx Vivado