Question: 1. Design 4-bit up/down counter using Verilog and write a testbech to verify the functionality of the counter. If input up_down is 1, your counter

1. Design 4-bit up/down counter using Verilog and write a testbech to verify the functionality of the counter. If input up_down is 1, your counter should start counting up, else it should count down. The output of the counter is zero, when reset signal is set.

2. Submission: Verilog Code for your design and test-bench, Include your waveform from simulation.

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