1. Design and Implement the MIPS Single Cycle Processor for the JAL instruction Draw the Datapath to implement this instruction. You can add logic elements such as Multiplexers, Sign-extender etc. in your design. The MIPS state elements are as follows: CLK CLK CLK PC PC 22 WE 32 A1 WE3 RD1 RD2 32 A RD Instruction Memory 32 A2 32 32 32 A RD Data Memory WD 5 A3 Register WD3 File 32 Also, show the main decoder truth table like Table 7.3 and Table 7.4 of the textbook. Table 7.4 Main decoder truth table enhanced to support addi Instruction Opcode Reg Write Reg Dst ALUSTC Branch Mem Write MemtoReg ALUOP R-type 000000 1 1 0 0 0 0 10 lw 100011 1 0 1 0 0 1 00 SW 101011 0 Ix 1 0 1 00 beg 000100 0 X 0 1 0 X 01 addi 001000 1 0 1 0 0 0 00