This is table 7.4

2. Design and Implement the MIPS Single Cycle Processor for the JR instruction. Draw the Datapath to implement this instruction. You can add logic elements such as Multiplexers, Sign-extender etc. in your design. The MIPS state elements are as follows: CLK CLK CLK PC PC WE3 WE A1 RD1 RD2 32 A RD Instruction Memory A2 A RD Data Memory WD WD3 Register File Also, show the main decoder truth table like Table 7.3 and Table 7.4 of the textbook. RegWrite Reg Dst ALUSrc Branch Instruction R-type lw Opcode 000000 100011 Mem Write MemtoReg ALUOP 0 10 1 0 0 1 0 1 0 0 1 00 SW 101011 0 1 0 1 X 00 beg 000100 0 0 1 0 01 addi 001000 1 0 1 0 0 0 00