1) For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Complete the table for other parameters. Consider 32-bit for each word. Tag Index OffsetTotal bits of cache*Cache line Number of words Data bits of cache** size for each block (in bits) b31-b12 b31-b11 b31-b13b12-b6 b11-b4 B10-b5 b3-b0 b4-b0 b5-b0 *Total bits of cache valid bittag bits for each block+ block bits for data **Data bits of cache block bits for data