1. Given an unpipelined processor with a 30ns cycle time and pipeline latches with 1 ns latency, a pipelined version of the processor with 5 stages has been formed if the datapath logic is evenly divided among the pipeline stages.

a. Calculate the cycle times of the pipelined processor

b. How much is the unpipelined latency?

c. Calculate the latency of pipelined processor.

d. Compare the throughput of the unpipelined and pipelined processor.

2. Identify all of the pipelining hazards in the following instruction sequence.

BEQ r10, #2, r11

DIV r11, r7, r3

SUB r3, r4, r8

OR r10,r7, r0

ASH r2, r14, r6