1) Modify the RAM code to a parameterized design and write the testbench to test the 2^8 x8 RAM by writing alternating 0s and 1s in the even address and alternating 1s and 0s in the odd address and then read it back to compare. Then swap the patterns and test again.

module RAM(CS, WE, OE, ADDR, DATA); input CS; input WE; input OE; input [3:0] ADDR; inout [3:0] DATA;

reg[3:0] RAM1[0:15];

assign DATA = (CS == 1'b1 | WE == 1'b0 | OE == 1'b1)? 4'bZZZZ : RAM1[ADDR]; //read from RAM

always_comb begin @(negedge WE) if(CS == 1'b0) begin RAM1[ADDR] <= DATA; end end endmodule