1) Using the multicycle datapath and the finite state machine of the controller for that datapath and assuming that a clock cycle is defined from the bottom of a rising edge to the bottom of the next rising edge, complete the table showing the data that will be stored (or is still stored) in each register on the next rising edge of the clock during the execution of the following MIPS instructions. All register data should be specified in hexadecimal. All data values, addresses, and offsets are given in hexadecimal. The register contents at the beginning of the execution of each instruction are listed below. Assume each instruction below is executed independently and each has the same starting data in the registers (i.e. no instruction impacts any of the others). If the contents of a register are not known, use a '?" in the appropriate cell. If an instruction does not use a particular clock cycle, put an 'X' in the cells for that clock cycle. Do not leave any cells blank. (50 points) Ss0 00 00 00 01 $s1 = 00 00 50 00 $s2 = 00 00 11 11 $s3 = 000001 00 $s4 = 00 00 1 1 12 $s5 = 00 00 00 1 1