Question: 1. Write a VHDL module for an 8-bit signed summation (using 2s complement numbers). The inputs dont have a carry, and the outputs are: the

1.Write a VHDL module for an 8-bit signed summation (using 2s complement numbers). The inputs dont have a carry, and the outputs are: the Sum (8-bit), the Carry (9-bit), and the Overflow indicator (1-bit). Then write a test bench for it. You must test the following cases:

(a) A <= "00000000"; B <= "01010101";

(b) A <= "10111111"; B <= "10101010";

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