$2.[35$ pts$]$

a$.[20$ pts$]$ Design a full subtractor $($which is similar to a full adder$)$ that performs subtraction between two $1-$bit numbers. As the inputs, the circuit has a minuhend bit, a subtrahend bit and a previous borrow bit. As the outputs, the circuit has the result bit and the next borrow bit. You are allowed to use only two $3-$to$-8$ decoders and a minimum number of OR gates. Complements of the variables, logic levels $1$ and $0$ are available. As an example,

b$.[15$ pts$]$ Design a synchronous modulo$-2$ adder, e$.$g$.,$