2) Simulate a 16 word cache with four words per block, direct mapped. a) For each address, list the six bit binary and indicate H for hit, M for miss. b) Draw the cache showing cache binary address and cache contents after all addresses have been processed. Use (1) for the contents of memory address 1, (4) for the contents of memory address 4, etc. Show valid bit and tag. Typical format for partial data at end of sequence eight word cache one word per block sixteen word cache four words per block data v tag data v tag 00 01 1011 000 | II 001 I I 010 I 011 1001| (11) | 100 | I 101 |I I I 110 I I 00 I 01 I 10 1 008)9) (10) (11) | The last address, decimal 11, has its contents shown in the cache (You do not get points for this entry.) 2) Simulate a 16 word cache with four words per block, direct mapped. a) For each address, list the six bit binary and indicate H for hit, M for miss. b) Draw the cache showing cache binary address and cache contents after all addresses have been processed. Use (1) for the contents of memory address 1, (4) for the contents of memory address 4, etc. Show valid bit and tag. Typical format for partial data at end of sequence eight word cache one word per block sixteen word cache four words per block data v tag data v tag 00 01 1011 000 | II 001 I I 010 I 011 1001| (11) | 100 | I 101 |I I I 110 I I 00 I 01 I 10 1 008)9) (10) (11) | The last address, decimal 11, has its contents shown in the cache (You do not get points for this entry.)