3. [15pts). Design the full adder circuit, assuming the input signals are Xi , Yi, G; the output signals are S and Cit1 The problems are: A: Figure out the logic expression of Sand Ci+1. [7pts] B: Implement the circuit using gates and draw the diagram. [8pts] 4. [15pts). Consider the circuit in Figure 1. Now the D and Clock are applied to the circuit, the problems are: A: Write the name of the three storage units. [3pts] B: Describe the functional differences of the three storage units. [6pts] C: Draw waveforms for the Qas Qo, and Qc signals in Figure 2. (The delay of logic gates could be ignored.) [6pts] IN D D Q Clock Clk Q D Q Q D Q ac Figure 1 Clock D % Figure 2