Question: 3. (30%) Write the Verilog code for the following circuit. (define only one module and do not use structural coding style) *** note that A,

3. (30%) Write the Verilog code for the following circuit. (define

3. (30%) Write the Verilog code for the following circuit. (define only one module and do not use structural coding style) *** note that A, B,W and Y are 5-bit inputs each ... A(4:0) 0 IN1 B(4:0) GT_EQU COMP SEL LESS W (4:0) 0 IN2 Y (4:0) if IN1 > = IN2, GT_EQU=1 if IN1

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