3. Complete the datapath and control for a new instruction. AIDM {cm(rd(rs)] Mem[r:2) on the given partial processor by showing all necded clemcnts and stenals Istimate the critical path delay by assuming that the instruction and data memory cach require 5, a tegister file and LU each require 2, and all other elements require 1 . The instruction, ADIMem, adds the content of register rs 1 to the content of data memory addressed by rs 2 and the result to be stored in a register rd (X[rd] - X[rs I] + Mem[rs2]). Assume the instruction is executed in one clock cycle