$3.$ Design a circuit that is a serial even parity generator. The circuit has two bits of input $\backslash ($ x $\backslash )$ and s $,$ where x is the data input and s is the start. The input number is applied bit$-$by$-$bit to the $\backslash ($ x $\backslash )$ input. The start signal $\backslash ($ s $\backslash )$ is supposed to be set to $1$ by the user to indicate the start of a new number. The new number's first bit is applied at the same time as $\backslash (\backslash$mathrm$\{$s$\}=1\backslash ).$ A signal $\backslash (\backslash$mathrm$\{$s$\}=0\backslash )$ implies that the old number is continuing and x is the next bit of the old number. There is one output bit p which outputs the even parity bit of the number seen so far beginning from the cycle of the most$-$recently seen $\backslash ($ s$=1\backslash )$ signal. In this way, this circuit can be used to compute the even parity of numbers of any length desired by the user. At startup, until the first $\backslash ($ s$=1\backslash )$ is seen, the output is undefined. Design a Moore machine using JK flip$-$flops. Use a formal design procedure. Draw the resulting circuit. Recall that an even parity bit is such a bit that makes the number of $1$ s in the number seen so far, including the parity bit, to be even $($i$.$e$,$ the number of bits in the number seen so far is odd$).$