$4\mathrm{.}16\mathrm{.}1$

In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:

Also, assume that instructions executed by the processor are broken down as follows:

What is the clock cycle time in a pipelined and non$-$pipelined processor?

$4\mathrm{.}16\mathrm{.}4$

Assuming there are no stalls or hazards, what is the utilization of the data memory?

What is the clock cycle time in a pipelined and non$-$pipelined processor?

$4\mathrm{.}16\mathrm{.}4$

Assuming there are no stalls or hazards, what is the utilization of the data memory?

$4\mathrm{.}3\mathrm{.}3$ What fraction of all instructions use the sign extend?

$4\mathrm{.}3\mathrm{.}4$ What is the sign extend doing during cycles in which its output is not needed?