4 Circuit Timing: 20 Points Consider the counter circuit in the following figure (This is a synchronous counter with parallel load). Assume that T, (setup time) is 3ns and T, (hold time) is Ins for the flip flops. Assume that Tpd (propogation delay) through each gate (AND, XOR, and MUX) is Ins. What is the maximum clock frequency for which the counter will operate correctly? Why? Enable Do D. D2 D3 Out put cary Load Clock