424 Chapter 4 The Processor Exercise 4.16 The first three problems in this exercise refer to the following MIPS instruction: Instruction SW R16,-100(R6) 4.16.1 [5] As this instruction executes, what is kept in each register located between two pipeline stages? 4.16.2 [51 Which registers need to be read, and which registers are actually read? 4.16.3 [5] What does this instruction do in the EX and MEM stages