part (B) only

Exercise 4.1 Different instructions utilize different hardware blocks in the basic single-cyde implementation. The next three problems in this exercise refer to the following instruction: Instruction Interpretation a. AND Rd.RS.RU SW Rt.Offs(Rs) Regt Ral-Reg[RS] AND Rogt Rt) Men[ Reg Rs 1+01 1s1-RegER] b. 4.1.1 (5) What are the values of control signals generated by the control in Figure 4.2 for this instruction 4.1.2 (5) Which resources (blocks) perform a useful function for this instruction? 4.1.3 [10] Which resources (blocks) produce outputs, but their outputs are not used for this instruction? Which resources produce no outputs for this instruction? 410 Chapter 4 The Processor Different execution units and blocks of digital logic have different latencies (time needed to do their work). In Figure 4.2 there are seven kinds of major blocks. Laten- cies of blocks along the critical (longest-latency) path for an instruction determine the minimum latency of that instruction. For the remaining three problems in this exercise, assume the following resource latencies Max ALU Reg Control 200ps 70 250ps 750 200ps Hem Added D-lem 2009 . 1. 250 300 S00 300 4.1.4 [5] What is the critical path for an MIPS AND instruction? 4.1.5 151 What is the critical path for an MIPS load (LD) instruction? 4.1.6 110) What is the critical path for an MIPS BEQ instruction! 304 Chapter 4 The Processor Branch Add Add xe3 ALU operation Data PC Address Instruction Register # Registers Register Mem Write Address ALU Zero Instruction memory Data memory Register # RogWrite Data MemRead Control FIGURE 4.2 The basic implementation of the MIPS subset, including the necessary multiplexors and control lines. The top multiplexer("Mox") controls what value replaces the ICC 4o the branch destination with