4.8 In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies: IF ID EX MEM WB 250ps 350ps 150ps 300ps 200ps Also, assume that instructions executed by the processor are broken down as follows: alu 45% beq Iw SW 20% 20% 15% 4.8.1 [5] What is the clock cycle time in a pipelined and non-pipelined processor? 4.8.2 [10] $4.5> what is the total latency of an LW instruction in a pipelined and non-pipelined processor