$5\mathrm{.}26$ Chip multiprocessors $($CMPs$)$ have multiple cores and their caches on a single chip. CMP on$-$chip L$2$ cache design has interesting trade$-$offs. The following table shows the miss rates and hit latencies for two benchmarks with private vs$.$ shared L$2$ cache designs. Assume L$1$ cache has a $3\%$ miss rate and a $1-$cycle access time. Private Shared Benchmark A misses$-$per$-$instruction $10\%4\%$ Benchmark B misses$-$per$-$instruction $2\%1\%$ Assume the following hit latencies: Private Cache Shared Cache Memory $520180$

$5\mathrm{.}26\mathrm{.}1[15]<5\mathrm{.}13>$ Which cache design is beer for each of these benchmarks? Use data to support your conclusion.

$5\mathrm{.}26\mathrm{.}2[15]<5\mathrm{.}13>$ Off$-$chip bandwidth becomes the boleneck as the number of CMP cores increases. How does this boleneck affect private and shared cache systems differently? Choose the best design if the latency of the first off$-$chip link doubles.

$5\mathrm{.}26\mathrm{.}3[10]<5\mathrm{.}13>$ Discuss the pros and cons of shared vs$.$ private L$2$ caches for both single$-$threaded, multi$-$threaded, and multiprogrammed workloads, and reconsider them if having on$-$chip L$3$ caches.

$5\mathrm{.}26\mathrm{.}4[15]<5\mathrm{.}13>$ Would a non$-$blocking L$2$ cache produce more improvement on a CMP with a shared L$2$ cache or with a private L$2$ cache? Why?

$5\mathrm{.}26\mathrm{.}5[10]<5\mathrm{.}13>$ Assume new generations of processors double the number of cores every $18$ months. To maintain the same level of per$-$core performance, how much more off$-$chip memory bandwidth is needed for a processor released in three years?

$5\mathrm{.}26\mathrm{.}6[15]<5\mathrm{.}13>$ Consider the entire memory hierarchy. What kinds of optimizations can improve the number of concurrent misses?