6. Exercise 4.3: Performance of Single Cycle Processor (5 points). Assume that the latencies of I- Mem, Add, Mux, ALU, Regs, D-Mem, and Control blocks in the single-cycle datapath above are 300 ps, 80 ps, 30 ps, 100 ps, 80 ps, 300 ps, and 40 ps respectively. Now consider the addition of a multiplier to the ALU. This will double the latency of the ALU. However, the instruction count is expected to reduce by 20% on average, since we will no longer need to emulate the MUL instruction. Quantitatively analyze the profitability of this investment