6. Given a nonpipelined processor A that requires 50 units of time to complete an instruction and a pipelined processor B that requires the 4 stages as shown in the table below (assume any pipeline overhead has already been added to the stage times, so they add up to more than 50 units of time) to complete an instruction but allows for overlaping execution. Give an equation in the boxes below that details how many units of time Processor A and Processor B require to execute 100 instructions assuming no stalls. (10 points, 5 points each equation) Stage 4 Time Units 12 15 13 13 Proc A Proc B 7. For the following y86 instruction stream, draw the pipeline stage diagram (shows in which cycle each instruction enters a particular stage of the pipeline). Assume the base pipelined processor with all possible forwarding paths and the 5 stage pipeline discussed in class with stages F, D, E, M, WB (5 points) Cycle --> 0 2 4 6 1: mrmovq (%rbp), %rbx 2: addq %rbx, %rax