$7.$

According to the datasheet, flip$-$flops have a clock$-$to$-$Q contamination delay of $30$ ps and a propagation delay of $50$ ps $.$ They also require a setup time of $30$ ps and a hold time of $30$ ps $.$ Each logic gate has a propagation delay of $70$ ps and a contamination delay of $60$ ps $.$ For the digital logic to operate at $2$ GHz $,$ what is the maximum number of gates that can be connected in the critical path of the combinational logic? Note that $\backslash (1\backslash$mathrm$\{$ps$\}=10^\{-12\}\backslash$mathrm$\{$~s$\}=0\mathrm{.}001\backslash$mathrm$\{$~ns$\}\backslash ).$