7.33 A RISC processor executes the following code. There are no data dependencies. ADD r0,rl,r2 ADD r3,r4,r5 ADD r6,r7,r8 ADD r9,r10,rll ADD rl2,r13,r14 ADD rl5,r16,r17 a. Assuming a four-stage pipeline (fetch, operand fetch, execute, and write) what registers are being read during the sixth clock cycle and what register is being written? b. Assuming a five-stage pipeline (fetch, operand fetch, execute, write, and store) what registers are being read during the sixth clock cycle and what register is being written? 7.43 Branch instructions may be taken or not taken. What is the relative frequency of taken to not taken, and why is this so? 7.44 What is branchless computing? 7.45 What is a delayed branch and how does it contribute to minimizing the effect of pipeline bubbles? Why are delayed branch mechanisms less popular then they were? 7.46 How does branch prediction reduce the branch penalty? When calculating the cost of a branch, we derived two expressions. One was 1 -b.p, and the other was (1 -p ) + p [lp + B(l -p )]. Demonstrate that these :re th/sam; result. 7.50 What is the difference between static and dynamic branch prediction