$($a$)$ Consider two different implementations of the same instruction set architecture. The instructions can be divided into four classes according to their CPI $($class A$,$ B$,$ C$,$ and D$).$ P$1$ with a clock rate of $2\mathrm{.}5$ GHz and CPIs of $1,2,3,$ and $3,$ and P$2$ with a clock rate of $3$ GHz and CPIs of $2,2,2,$ and $2.$