A CPU with a Tomasulo engine has two integer units (each capable of doing loads and stores), one floating point unit capable of doing both additions and multiplications. That unit has four reservation stations (fp1 to fp4) and can initiate a new operation every cycle. Its latency is three cycles per operation (addition or multiplication). That CPU can issue up to two instructions per cycle assuming no structural hazards. Loads have a latency of two cycles, all other integer instructions take only one cycle. There are six load reservation stations (lb1 to lb6) and the store buffer has sixteen entries. Branch instructions are statically predicted taken.

The code being considered is: Z[i] = a*X[i] + b*Y[i], all values are in double precision. Registers F2 and F3 hold the constants a and b respectively.

1.Complete the first table below for two loop iterations.

2.Complete the second table showing which unit will be writing which register at what cycle.

Estimate the number of cycles as a functional of the loop count N.

i	Instruction	Issue	Exec Starts	Exec Complete	Write Result	Comments
1	LD F0,0(r1)	1	2	3	4
1	LD F1,0(r2)
1	MULD F4,F0,F2
1	MULD F5,F1,F3
1	ADDD F6,F4,F5
1	SD F6,0(r3)
1	ADD r1,r1, -8
1	ADD r2,r2, -8
1	ADD r3,r3, -8
1	BNEZ r1, loop
2	LD F0,0(r1)
2	LD F1,0(r2)
2	MULD F4,F0,F2
2	MULD F5,F1,F3
2	ADDD F6,F4,F5
2	SD F6,0(r3)
2	ADD r1,r1, -8
2	ADD r2,r2, -8
2	ADD r3,r3, -8
2	BNEZ r1, loop

cycle	F0	F1	F4	F5	F6
4	lb1