Question: A s ' slage pipelined procersor has IF , RD , E x , MEM, W B . stages take 1 clock cycle each for

A s' slage pipelined procersor has IF, RD,Ex,MEM,WB. stages take 1 clock cycle each for any instructions. Solve the question without operand forwarding & vell no. I cycles needed to execule the following instrudion.
ADD,R5,R0,R1
MUL R6,R2,R5
SUB R5,R3,R6
Div,R6,R5',R4
STORE R6,x
Kindly draw the pipeline diagram to explain it
A s ' slage pipelined procersor has IF , RD , E x

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