Question $2(40\%)-$ Consider a MIPS processor that uses the five$-$stage pipeline

described in class $($IF$,$ ID$,$ EXE, MEM, WB$).$ The processor is used to execute the

following sequence of instructions:

$SW$ $$s0,80($$$s3)$

$LW$ $$s4,8($$$s0)$

ADDI $$s5,$ $$s4,10$

AND $$s6,$ $$s4,$ $$s4$

ADD $$s7,$ $$s4,$ $$s5$

Pipelined execution: assume that the clock cycle is $2ns.$

A$.$ Indicate the data dependences that result due to the execution of this

instructions sequence. The data dependency occurs when an instruction

produces a value in a given pipeline stage, and a subsequent instruction

consumes that value in another pipeline stage.

B$.$ Which hazard type occurs due to the data dependency described in A$?$

C$.$ Show the pipelined execution if the pipeline has no bypassing, and the registers

cannot be read and written in the same clock cycle. Compute the total

execution time. To answer this question, and the other similar questions, you

need to fill the chart below. You can expand the chart vertically and horizontally

as needed. Make sure to insert the NOP instructions when needed.

D$.$ Show the pipelined execution if the pipeline has no bypassing, and the registers

can be read and written in the same clock cycle. Compute the total execution

time.

E$.$ Show the pipelined execution if the pipeline supports bypassing, and the

registers can be read and written in the same clock cycle. Compute the total

execution time.

F$.$ Compute the speedup achieved by the pipelined execution that implements

bypassing and allows the registers to read and write in the same clock cycle

$($point E$)$ compared to the pipelined execution that does not implement

bypassing and does not allow the registers to read and write in the same clock

cycle $($point C$).$

Serial execution:

G$.$ Assume that of all execution stages $($IF$,$ ID$,$ EXE, MEM, WB$)$ requires the same

time $(2$ ns$).$ What is the length of the clock cycle that should be used if a single$-$

cycle processor $($i$.$e$.$ unpipelined processor$)$ is used to run the instructions

listed above instead of the pipelined processor? Also, Compute the total

execution time that is required to run the five instructions listed above.

$H.$ What is the speedup achieved by the pipelined execution that implements

bypassing and allows the registers to read and write in the same clock cycle

$($point E$)$ compared to the unpipelined execution $($point G$)?$