A simple cache model, 1 level only, is shown in the figure below. Tp is the average access time from the processor view. Tc is the cache access time. Tm is the memory access time. hrate is the cache hit rate. Assume hrate = 99% and the cache access time is 1/400 of the memory access time. What is the cache access time if the average access time from the processor view is Tp=5ns. (Hints: think about the relations among Tp, Tc and Tm)

Figure 2. A Simple 1 Level Cache Model

Processor Cache Memory