a) Sketch a 3-input NOR gate with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter. b) Compute the worst case rising and falling propagation delays (in term of R and C) of the NOR gate driving h identical NOR gates in one of their inputs using the Elmore delay model. Assume that every source or drain has fully contacted diffusion when making your estimate of capacitance. c) Compute the best-case contamination delay of the NOR gate? When does it happen? d) If C=2fF/um and R=10 k 2* um in a 0.6m process, what is of a fanout of 3 NOR gate worst case and best case falling delay.