A SRAM has an $8-$bit data bus and a $5-$bit address bus. The SRAM function table is shown below:

$.$

The CS$,$ WE$,$ and OE signals in the above function table are high active. Design the above SRAM in VHDL

library ieee;

use ieee.std$\_$logic$\_1164.$all;

use ieee.std$\_$logic$\_$unsigned.all;

entity ram is

port $($ address :$\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_$;

data :$\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_$ ;

cs : $\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_$;

we : $\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_$;

oe : $\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_)$;

end ram;

architecture beh$\_$ram of ram is

end beh$\_$ram;