Assume a five-stage single-pipeline microarchitecture (fetch, decode, execute, memory, write-back) and the code in figure below. All ops are one cycle except LW and SW, which are 1 + 2 cycles, and branches, which are 1 + 1 cycles. There is no forwarding. Show the phases of each instruction per clock cycle for one iteration of the loop. Assume a dynamic branch predictor. How many cycles are lost on a correct prediction?

Loop: LW R3, 0(R0)

LW R1, 0(R3)

ADDI R1, R1, #1

SUB R4, R3, R2

SW R1, 0(R3)

BNZ R4, Loop