Assume a five-stage single-pipeline microarchitecture (fetch, decode, execute, memory, write-back) and the code in figure below. All ops are one cycle except LW and SW, which are 1 + 2 cycles, and branches, which are 1 + 1 cycles. There is no forwarding. Show the phases of each instruction per clock cycle for one iteration of the loop. How many clock cycles per loop iteration are lost to branch overhead?