Assume that the following RISC code is executed on a pipelined processor with a $5-$stage pipeline with full forwarding and a "always$-$taken" branch predictor. Draw the pipeline diagram and report number of clock cycles it takes to execute this sequence of instructions.

Note: Result of branch is determined in EXE stage. Comments denote the true situation.

LABEL$1$: $\backslash (\backslash$quad $\backslash )$ lw x$1,40($x$6)$

beq $\backslash ($ x $2,$ x $3\backslash ),$ LABEL$2\backslash$# Taken

add $\backslash (\backslash$mathrm$\{$x$\}1,\backslash$mathrm$\{$x$\}6,\backslash$mathrm$\{$x$\}4\backslash )$

LABEL$2$: beq x$1,$ x$2,$ LABEL$1\backslash$# Not Taken

sw x$2,20($x$4)$

and $\backslash (\backslash$mathrm$\{$x$\}1,\backslash$mathrm$\{$x$\}1,\backslash$mathrm$\{$x$\}4\backslash )$