We assume that the MIPS code is executed on a pipelined processor with a $5-$ stage pipeline, full forwarding, and a branch predictor $($The $$beq$$ in label$1$ predicts branch non$-$taken for the first time, and then it predicts taken for the following execution. The second $$beq$$ in this code always predicts branch taken, assuming that all the branch prediction are right$).(1)$ Draw the pipeline execution diagram for this code, assuming there are no delay slots and that branches execute in the EX stage.