Assume the following processor configuration: a dedicated L1 cache for instructions (IL1)

and a L1 cache for data (DL1), a shared L2 cache that serves as an intermediate level between

each of the L1 caches and the main memory.

Out of the total instructions executed in this processor, assume load/store instructions

comprise of 25% of the total instructions.

Cycle Time 1ns

Hit Time to L1(I-L1 or D-L1) and return the data to the processor 1 cycle

IL1 miss rate 8%

DL1 miss rate 15%

Hit Time to L2 and return the data to the L1(I-L1 or D-L1) 6 cycles

L2 miss rate 30%

Main Memory Access Time from L2 50 cycles

1. What is the average memory access time?

2. Assume CPI = 1 if the processor has no memory stalls. Without the caches, each memory

access would take 52 cycles. What is the CPI of the processor without any caches?

3. Assume CPI = 1 if the processor has no memory stalls. What is the CPI of processor with

the all the caches? Remember that it takes 50 cycles to access memory from L2.