Question: Assume two processor designs with the latencies specified in the following table. IF ID EX MEM WB Processor A 200ps 110ps 160ps 200ps 110ps Processor

Assume two processor designs with the latencies specified in the following table. IF ID EX MEM WB Processor A 200ps 110ps 160ps 200ps 110ps Processor B 180ps 120ps 140ps 300ps 100ps a.) (20 pts) What is the cycle time for Processor A and Processor B without pipelining? b.) (25 pts) With 5-stage pipeline, what is the cycle time for A and B assuming each pipeline register adds 10ps latency

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