Assuming that $S1,S2,$ and $S3$ are the select control inputs of an

Arithmetic Logic Unit $($ALU$)$ whose data inputs are A and B$,$

implement the ALU using gate$-$level symbols, for the following

functional description of its output $F($where $\text{'}$ denotes

complementation$).$ Build a hierarchical mux tree using $2-$input

muxes.