B. Consider a 32-bit physical memory space and a 32 KiB 2-way associative cache with LRU replacement. You are told the cache uses 5 bits for the offset field. Write in the number of bits in the tag and index fields in the figure below. (2 points) Tag Index Offset 5 bits 31 0 C. Assume the same cache as in the previous part. (4 points) int ARRAY SIZE 641024; int arr[ARRAY_SIZE]: // arr is aligned to a cache block /* loop 1 */ for (int i = 0; ? = 0; i-= 8) arr [i+1] = arr [i]; i; - - i. What is the hit rate of loop 1? What types of misses, if any, occur as a result of loop 1? (2 points) i. What is the hit rate of loop 2? What types of misses (of the 3 Cs), if any, occur as a result of loop 22 (2 points)