need part C)

B. Consider a 32-bit physical memory space and a 32 KiB 2-way associative cache with LRU replacement You are told the cache uses 5 bits for the offset field. Write in the number of bits in the tag and index fields in the figure below. (2 points) Tag Index Offset 5 bits 31 C. Assume the same cache as in the previous part. (4 points) int ARRAY_SIZE = 64 * 1024; int arr[ARRAY SIZE] / arr is aligned to a cache block /* loop 1 */ for (int ? 0; ? -0; i -- 8) arri+1-arr[i; i. What is the hit rate of loop 1? What types of misses, if any, occur as a result of loop 1? (2 points) ii. What is the hit rate of loop 2? What types of misses (of the 3 Cs), if any, occur as a result of loop 2? (2 points)