b$.$ In the full adder circuit shown below, all gates are assumed to have the

same gate$-$delay D$.$

Figure $5$b: Full adder circuit

i$.$ Write the Boolean expression of:

$G_i$ and $P_i$ in terms of $a_i$ and $b_i,$

$C_{i+1}$ in terms of $G_i,P_i$ and $C_i,$ and

$S_i$ in terms of $P_i$ and $C_i.$

How long is the longest propagation delay

from $a_i$ and $b_i$ to $S_i,$

from $a_i$ and $b_i$ to $C_{i+1}$ and

from $C_i$ to $C_{i+1}?$

$(6$ marks$)$

ii$.$ A $16-$bit ripple carry adder is realized using $16$ full adders shown in

Figure $5b,$ with $C_0=0.$ What is the worst$-$case delay $($in number of

gate$-$delay D$)$ for this $16-$bit adder? Explain your calculation clearly.

$(4$ marks$)$

iii. Compare the advantages and disadvantages of asynchronous ripple

carry adder and Carry Look ahead adder?

a$.$ The five stages of a microprocessor have the following latencies:

If pipelining were to be used, each pipeline stage requires additional $20$ps

$($picoseconds$)$ for the registers between pipeline stages

i$.$ For a non$-$pipelined processor: what is the cycle time?

What is the latency of an instruction? What is the throughput?

ii$.$ For a pipelined processor: What is the cycle time?

What is the latency of an instruction? What is the throughput?

iii. If one of the pipeline stages can be split into $2$ equal halves, which

one would be the choice to give the best throughput? What is the new

cycle time? What is the new latency? What is the new throughput?