Procedure Employ structural VHDL in your design by implementing the circuit shown in Figure 1 using port map statements to implement the AND and OR gates. Use concurrent signal assignment statements to obtain the required negated values of the input signals. Write entity-architecture descriptions for the AND and OR gate components using concurrent VHDL (i.e. the and operator for the AND gate). You may use a concurrent signal assignment statement in your top-level code to negate the output which drives the LED output.

Use the following VHDL entity specification: library IEEE; use IEEE.std_logic_1164.all; entity sum_of_minterms is port( a,b,c : in std_logic; output : out std_logic); end sum_of_minterms;

This is what i have so far but i keep getting errors.

library IEEE; use IEEE.std_logic_1164.all;

entity sum_of_minterms_tb is end sum_of_minterms_tb;

architecture test of sum_of_minterms_tb is component sum_of_minterms is port (a,b,c: in std_logic; output: out std_logic); end component;

signal y1, y2, y3 : std_logic; begin u1: sum_of_minterms port map (y1

library IEEE; use IEEE.std_logic_1164.all;

entity sum_of_minterms is port (a,b,c: in std_logic; output: out std_logic); end entity;

architecture minterms_arch of sum_of_minterms is begin output Introduction Consider the following truth table defning a three vaiable Boolean function: Table 1: Some arbitrary Boolean Function. OUT The function may be expressed in sum-of-minterms form as: OUT = ABC + AB C + A B C . The gate level hardware implementation of the function is shown in Figure 1 OUT Figure 1: Two-level sum of minterms hardware implementation