Question: Can someone help me write a test bench in VHDL for the following VHDL code which test all cases for this 4 to 1 MUX?

Can someone help me write a test bench in VHDL for the following VHDL code which test all cases for this 4 to 1 MUX?

Can someone help me write a test bench in VHDL for the

library ieee; use eee. std-logic-1164. all entity MUX is port (In0, In1, In2, In3: n std_logic sel: in std logic vector (1 down to 0) ob out std_logic end MUX architecture behavioral of MUX is begin process (In0, In1 In2, In3, sel) Begin if (sel 00 t hen ob In0 elsif (sel 1") hen ob In elsif (sel 10" hen ob In2 else ob In3 end if end process; end behavioral

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