Can you please do the Prelab: STATE GRAPH AND STATE TABLE

Lab for Computer Architecture CENG 3151 Lab #2: Moore Sequential Circuit 1. Requirement A Moore sequential circuit has one input a occurs, the output becomes 'I and remains '1 until the sequence '011' occu which the output returns to '0'. The output then remains '0' until a'011' occurs the third time etc.... nd one output. When the input sequence 'o11 Input 0 0 01 1 0 1 001 1 1 Output 0 0 0 01 1 1 0 0 0 0 0 0 1 1 Moore Sequential Circuit Reset CLK 2. Pre-lab State graph State table 3. Lab a. Design the circuit b. Simulate using Xilinx ISE simulator 4. Deliverables VHDL program VHDL test cases Waveform